1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device, and more particularly to a manufacturing method preferably used for a semiconductor device using SOI (Silicon on Insulation) technology.
2. Related Background Art
Conventionally, SOIs are known in a broad sense as technology, such as single crystal SOIs, used mainly in high-speed or three-dimensional ICs, and TFTs (Thin Film Transistors) which use thin film semiconductor layers, such as poly-Si or a-Si, and are mainly and preferably used as driving transistors for contact reading sensors or liquid crystal displays.
In the above technology, TFTs have conventionally gained attention in terms of low cost and the fact that they can be manufactured on large area substrates. However, recent demands for high performance and high precision contact reading sensors and the like have required TFTs with superior characteristics.
As a method of accomplishing such superior characteristics, the quality of a semiconductor layer of the TFT is improved to approach a single crystal. TFTs using poly-Si, with mobility higher than that of a-Si, have been recently realized.
Although endeavors have been made to improve the performance of the conventional TFT, the current conventional TFT, having a semiconductor layer formed by the poly-Si, is behind the single crystal SOI in terms of gain and leakage current characteristics. Furthermore, in contrast to the above single crystal SOI, in which seeds (seed crystals) are obtained from a single crystal substrate called SEG (Selective Epitaxial Growth) or LSPE, it is difficult for the TFT to grow a single crystal layer on the entire face of a glass substrate. For these reasons, as a method of improving the TFT characteristics, improvements in a device structure based on the manufacturing process have gained attention.
For example, in the conventional stacking process, as illustrated in FIG. 1, which is a schematic cross-sectional view, the semiconductor device in accordance with the conventional SOI is constructed in the following manner. A source region 2a as well as a drain region 2b, are previously formed on an insulating film. A semiconductor layer 3 and a gate insulating film 4 are then formed on the upper layer of the regions, followed a gate electrode 5 being formed on the upperlayer of the gate insulating film 4.
The construction such as the above one, however, poses problems in that variations in the effective gate length increase, and that the amount of overlapping between the gate and the drain also increases. For these reasons, in a semiconductor device in which an active element and a drive element are integrated with each other, when the manufacturing process inevitably generates an overlapped portion between the semiconductor layer 3 and the gate electrode 5, as in the TFT construction shown in FIG. 1, this overlapped portion assumes parasitic capacitance in driving the elements, thereby hindering high-speed driving.
To overcome such problems as the above ones, it is possible to adopt a process, such as a self alignment, which is utilized as a conventional IC process. In this case, the structure of a semiconductor device is, for example, like the one illustrated in FIG. 2, which is a schematic cross-sectional view. Direct introduction of the conventional IC process, such as the self alignment, however, causes the process to be complicated, and is not suitable for a glass substrate because of the need for a high temperature process. This leads to the foremost problem of increased cost of the semiconductor. In addition, as illustrated in FIG. 2, a problem exists in that since an ion implantation process and a heat diffusion process are performed on the semiconductor layer 3 in order to form the source region 2a and the drain region 2b, diffusion takes place in a horizontal direction, not allowing the elimination of the overlapped parasitic capacity.